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<div class="title">xcsi2tx_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:ga8f58282f5d1917ec080b9b210aad48a6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga8f58282f5d1917ec080b9b210aad48a6">XCSI2TX_HW_H_</a></td></tr>
<tr class="memdesc:ga8f58282f5d1917ec080b9b210aad48a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="group__csi2tx.html#ga8f58282f5d1917ec080b9b210aad48a6">More...</a><br/></td></tr>
<tr class="separator:ga8f58282f5d1917ec080b9b210aad48a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac7a1f2d7c25c0f7238931c4941af0da8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#gac7a1f2d7c25c0f7238931c4941af0da8">XCSI2TX_GSP_MASK</a>&#160;&#160;&#160;0x00000001F</td></tr>
<tr class="memdesc:gac7a1f2d7c25c0f7238931c4941af0da8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of GSPs can be safely written to GSP FIFO, before it goes full.  <a href="group__csi2tx.html#gac7a1f2d7c25c0f7238931c4941af0da8">More...</a><br/></td></tr>
<tr class="separator:gac7a1f2d7c25c0f7238931c4941af0da8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Device registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register sets of MIPI CSI2 Tx Core </p>
</div></td></tr>
<tr class="memitem:ga946323f75e230f56d7fc2a9640bd8ab1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga946323f75e230f56d7fc2a9640bd8ab1">XCSI2TX_CCR_OFFSET</a>&#160;&#160;&#160;0x00000000</td></tr>
<tr class="memdesc:ga946323f75e230f56d7fc2a9640bd8ab1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core Configuration Register.  <a href="group__csi2tx.html#ga946323f75e230f56d7fc2a9640bd8ab1">More...</a><br/></td></tr>
<tr class="separator:ga946323f75e230f56d7fc2a9640bd8ab1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabb3185c624bf861b9d97e8dad49b3d48"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabb3185c624bf861b9d97e8dad49b3d48"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_PCR_OFFSET</b></td></tr>
<tr class="separator:gabb3185c624bf861b9d97e8dad49b3d48"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9367d74644fe257d2d9ef283bf81d327"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga9367d74644fe257d2d9ef283bf81d327">XCSI2TX_GIER_OFFSET</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga9367d74644fe257d2d9ef283bf81d327"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Register.  <a href="group__csi2tx.html#ga9367d74644fe257d2d9ef283bf81d327">More...</a><br/></td></tr>
<tr class="separator:ga9367d74644fe257d2d9ef283bf81d327"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab2d607c7c70706cdb08326d2f9d35396"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#gab2d607c7c70706cdb08326d2f9d35396">XCSI2TX_ISR_OFFSET</a>&#160;&#160;&#160;0x00000024</td></tr>
<tr class="memdesc:gab2d607c7c70706cdb08326d2f9d35396"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Status Register.  <a href="group__csi2tx.html#gab2d607c7c70706cdb08326d2f9d35396">More...</a><br/></td></tr>
<tr class="separator:gab2d607c7c70706cdb08326d2f9d35396"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2e9aa73ddca76ee93a3c18573a082f19"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga2e9aa73ddca76ee93a3c18573a082f19">XCSI2TX_IER_OFFSET</a>&#160;&#160;&#160;0x00000028</td></tr>
<tr class="memdesc:ga2e9aa73ddca76ee93a3c18573a082f19"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Enable Register.  <a href="group__csi2tx.html#ga2e9aa73ddca76ee93a3c18573a082f19">More...</a><br/></td></tr>
<tr class="separator:ga2e9aa73ddca76ee93a3c18573a082f19"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga98c70dd97a33a24cd5a1d80f9fe9d902"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga98c70dd97a33a24cd5a1d80f9fe9d902">XCSI2TX_SPKTR_OFFSET</a>&#160;&#160;&#160;0x00000030</td></tr>
<tr class="memdesc:ga98c70dd97a33a24cd5a1d80f9fe9d902"><td class="mdescLeft">&#160;</td><td class="mdescRight">Generic Short Packet Entry.  <a href="group__csi2tx.html#ga98c70dd97a33a24cd5a1d80f9fe9d902">More...</a><br/></td></tr>
<tr class="separator:ga98c70dd97a33a24cd5a1d80f9fe9d902"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga71d1e5d100d088c2482482878f868530"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga71d1e5d100d088c2482482878f868530">XCSI2TX_LINE_COUNT_VC0</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga71d1e5d100d088c2482482878f868530"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count for VC0.  <a href="group__csi2tx.html#ga71d1e5d100d088c2482482878f868530">More...</a><br/></td></tr>
<tr class="separator:ga71d1e5d100d088c2482482878f868530"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0416b10b41b6db1ec5a6ee91a79e7005"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga0416b10b41b6db1ec5a6ee91a79e7005">XCSI2TX_LINE_COUNT_VC1</a>&#160;&#160;&#160;0x00000044</td></tr>
<tr class="memdesc:ga0416b10b41b6db1ec5a6ee91a79e7005"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count for VC1.  <a href="group__csi2tx.html#ga0416b10b41b6db1ec5a6ee91a79e7005">More...</a><br/></td></tr>
<tr class="separator:ga0416b10b41b6db1ec5a6ee91a79e7005"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga62f584b06977c2aaa760aebee9ca4545"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga62f584b06977c2aaa760aebee9ca4545">XCSI2TX_LINE_COUNT_VC2</a>&#160;&#160;&#160;0x00000048</td></tr>
<tr class="memdesc:ga62f584b06977c2aaa760aebee9ca4545"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count for VC2.  <a href="group__csi2tx.html#ga62f584b06977c2aaa760aebee9ca4545">More...</a><br/></td></tr>
<tr class="separator:ga62f584b06977c2aaa760aebee9ca4545"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga23a3d797b27784997c641c8c8f0e984a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga23a3d797b27784997c641c8c8f0e984a">XCSI2TX_LINE_COUNT_VC3</a>&#160;&#160;&#160;0x0000004C</td></tr>
<tr class="memdesc:ga23a3d797b27784997c641c8c8f0e984a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count for VC3.  <a href="group__csi2tx.html#ga23a3d797b27784997c641c8c8f0e984a">More...</a><br/></td></tr>
<tr class="separator:ga23a3d797b27784997c641c8c8f0e984a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0de178a0d328d77c92f84bfa9eea9432"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0de178a0d328d77c92f84bfa9eea9432"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_GSP_OFFSET</b>&#160;&#160;&#160;0x00000078	/* &lt; GSP Status*/</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Bitmasks and offsets of XCSI_GIER_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the global interrupt enable bit. </p>
</div></td></tr>
<tr class="memitem:gac6230fca4f7c1adbda9fe1552ef4b3d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#gac6230fca4f7c1adbda9fe1552ef4b3d2">XCSI2TX_GIER_GIE_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gac6230fca4f7c1adbda9fe1552ef4b3d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Enable bit.  <a href="group__csi2tx.html#gac6230fca4f7c1adbda9fe1552ef4b3d2">More...</a><br/></td></tr>
<tr class="separator:gac6230fca4f7c1adbda9fe1552ef4b3d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga933b9901187f38c45f7b70e52e3344a3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga933b9901187f38c45f7b70e52e3344a3">XCSI2TX_GIER_GIE_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga933b9901187f38c45f7b70e52e3344a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for Global Interrupt Enable.  <a href="group__csi2tx.html#ga933b9901187f38c45f7b70e52e3344a3">More...</a><br/></td></tr>
<tr class="separator:ga933b9901187f38c45f7b70e52e3344a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga959e1d8eac158a90fdd7924124bf2bcc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga959e1d8eac158a90fdd7924124bf2bcc">XCSI2TX_GIER_SET</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ga959e1d8eac158a90fdd7924124bf2bcc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the Global Interrupts.  <a href="group__csi2tx.html#ga959e1d8eac158a90fdd7924124bf2bcc">More...</a><br/></td></tr>
<tr class="separator:ga959e1d8eac158a90fdd7924124bf2bcc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4eee0cf8e8f3042e85023c2c9e614704"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga4eee0cf8e8f3042e85023c2c9e614704">XCSI2TX_GIER_RESET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga4eee0cf8e8f3042e85023c2c9e614704"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the Global Interrupts.  <a href="group__csi2tx.html#ga4eee0cf8e8f3042e85023c2c9e614704">More...</a><br/></td></tr>
<tr class="separator:ga4eee0cf8e8f3042e85023c2c9e614704"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and offsets of XCSI_CCR_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used for the enabling/disabling and resetting the core of CSI2 Tx Controller </p>
</div></td></tr>
<tr class="memitem:ga726549ff15bda23c42a39cad8e1669e5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga726549ff15bda23c42a39cad8e1669e5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_CCR_COREENB_MASK</b>&#160;&#160;&#160;0x00000001 /* Enable/Disable core */</td></tr>
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<tr class="memitem:gaeb85dce251ac8b7f1f44ba560e3305bb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaeb85dce251ac8b7f1f44ba560e3305bb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_CCR_SOFTRESET_MASK</b>&#160;&#160;&#160;0x00000002 /* Soft Reset the core */</td></tr>
<tr class="separator:gaeb85dce251ac8b7f1f44ba560e3305bb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga050c1ee8bbdce93dd94af43c1407bc8a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga050c1ee8bbdce93dd94af43c1407bc8a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_CSR_RIPCD_MASK</b>&#160;&#160;&#160;0x00000004 /* Core ready */</td></tr>
<tr class="separator:ga050c1ee8bbdce93dd94af43c1407bc8a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga365bfb520f135bb4bb56ed4a552f6bc5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga365bfb520f135bb4bb56ed4a552f6bc5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_CCR_ULPS_MASK</b>&#160;&#160;&#160;0x00000008 /* ULPS */</td></tr>
<tr class="separator:ga365bfb520f135bb4bb56ed4a552f6bc5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf6b8fe661b78d795fcf3611582ef7503"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf6b8fe661b78d795fcf3611582ef7503"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_CCR_CLKMODE_MASK</b>&#160;&#160;&#160;0x00000010 /* Clock Mode */</td></tr>
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<tr class="memitem:gafcf8def5459794000772aaf53cb4c71f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafcf8def5459794000772aaf53cb4c71f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_CCR_COREENB_SHIFT</b>&#160;&#160;&#160;0 	/* Shift bit for Core Enable*/</td></tr>
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<tr class="memitem:ga67708ce79a9373342710f0aeee97b5f2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga67708ce79a9373342710f0aeee97b5f2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_CCR_SOFTRESET_SHIFT</b>&#160;&#160;&#160;1 	/* Shift bit for Soft reset */</td></tr>
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<tr class="memitem:ga57bca8bfbe0ad63fffd73dd0cf1a690b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga57bca8bfbe0ad63fffd73dd0cf1a690b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_CSR_RIPCD_SHIFT</b>&#160;&#160;&#160;2 	/* Bit Shift for Core Ready */</td></tr>
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<tr class="memitem:ga775ba2e4270ed52227edced140e20f64"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga775ba2e4270ed52227edced140e20f64"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_CCR_ULPS_SHIFT</b>&#160;&#160;&#160;3 	/* Shift bits for ulps */</td></tr>
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<tr class="memitem:ga3788a910bc4c8a75f61e921f984a3bb1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3788a910bc4c8a75f61e921f984a3bb1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_CCR_CLKMODE_SHIFT</b>&#160;&#160;&#160;4 	/* Shift bits for clock mode */</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Bitmasks and offset of XCSI2TX_PCR_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register reports the number of lanes configured during core generation and number of lanes actively used. </p>
</div></td></tr>
<tr class="memitem:gad0a745f32c903555cf7df3061bf5d6c9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad0a745f32c903555cf7df3061bf5d6c9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_PCR_LINEGEN_MASK</b>&#160;&#160;&#160;0x00008000 /* Line generation Mode */</td></tr>
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<tr class="memitem:gad43bf7b921fa34c7eba829716229cc33"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad43bf7b921fa34c7eba829716229cc33"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_PCR_PIXEL_MASK</b>&#160;&#160;&#160;0x00006000 /* Pixel Mode */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_PCR_MAXLANES_MASK</b>&#160;&#160;&#160;0x00000018 /* Maximum lanes in core */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_PCR_ACTLANES_MASK</b>&#160;&#160;&#160;0x00000003 /* Active  lanes in core */</td></tr>
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<tr class="memitem:ga6a14f86bc2a9474ec3a0071db4aee45d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga6a14f86bc2a9474ec3a0071db4aee45d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_PCR_LINEGEN_SHIFT</b>&#160;&#160;&#160;15 	/* Line generation */</td></tr>
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<tr class="memitem:ga6ca2cebab94aeca88e2316beef3ef65c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga6ca2cebab94aeca88e2316beef3ef65c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_PCR_PIXEL_SHIFT</b>&#160;&#160;&#160;13 	/* Pixel Mode */</td></tr>
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<tr class="memitem:ga1f0417288121bd4157beda42e4371387"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1f0417288121bd4157beda42e4371387"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_PCR_MAXLANES_SHIFT</b>&#160;&#160;&#160;3 	/* Max Lanes */</td></tr>
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<tr class="memitem:gac78977f0ddb422068a1f0d5af5cf6625"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac78977f0ddb422068a1f0d5af5cf6625"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_PCR_ACTLANES_SHIFT</b>&#160;&#160;&#160;0 	/* Active Lanes */</td></tr>
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<tr><td colspan="2"><div class="groupHeader">BitMasks interrupts</div></td></tr>
<tr class="memitem:ga612d2b33a8db8e718d2c9477b18f3fad"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga612d2b33a8db8e718d2c9477b18f3fad"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_IER_ALLINTR_MASK</b>&#160;&#160;&#160;0x0000003F /* All interrupts mask */</td></tr>
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<tr class="memitem:gabd86c2825d68e9f037b8cb08c130521d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabd86c2825d68e9f037b8cb08c130521d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_ISR_ALLINTR_MASK</b>&#160;&#160;&#160;0x0000003F /* All interrupts mask */</td></tr>
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<tr class="memitem:ga223995e1d54c0f09606264312f9be93a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga223995e1d54c0f09606264312f9be93a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_UNDERRUN_PIXEL_MASK</b>&#160;&#160;&#160;(1&lt;&lt;0)	/* Underrun Pixel */</td></tr>
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<tr class="memitem:ga4a23339836251388c591f7194bcb6cdb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4a23339836251388c591f7194bcb6cdb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_WRONG_DATATYPE_MASK</b>&#160;&#160;&#160;(1&lt;&lt;1)	/* Wrong data type */</td></tr>
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<tr class="memitem:gabb308707a3edf6a16a2accc9ecc018bb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabb308707a3edf6a16a2accc9ecc018bb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_LINE_BUFF_FULL_MASK</b>&#160;&#160;&#160;(1&lt;&lt;2)	/* Line buffer full */</td></tr>
<tr class="separator:gabb308707a3edf6a16a2accc9ecc018bb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga53bd7ae31025e7e21702d99a57c4a4a9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga53bd7ae31025e7e21702d99a57c4a4a9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_DPHY_ULPS_MASK</b>&#160;&#160;&#160;(1&lt;&lt;3)	/* Dphy ulps */</td></tr>
<tr class="separator:ga53bd7ae31025e7e21702d99a57c4a4a9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf9d48a903d8cae2056e50c07773d6c09"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf9d48a903d8cae2056e50c07773d6c09"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI_GPSFIFO_MASK</b>&#160;&#160;&#160;(1&lt;&lt;4)	/* GPS fifo full */</td></tr>
<tr class="separator:gaf9d48a903d8cae2056e50c07773d6c09"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga32dea0d9bf28275eec9656bc0beab692"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga32dea0d9bf28275eec9656bc0beab692"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI_INCORT_LANE_MASK</b>&#160;&#160;&#160;(1&lt;&lt;5)	/* Wrong lane configuration */</td></tr>
<tr class="separator:ga32dea0d9bf28275eec9656bc0beab692"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0044b3d448765635208740af525b7f8f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga0044b3d448765635208740af525b7f8f">XCSITX_LCSTAT_VC0_IER_MASK</a>&#160;&#160;&#160;(1&lt;&lt;8)</td></tr>
<tr class="memdesc:ga0044b3d448765635208740af525b7f8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC0 IER.  <a href="group__csi2tx.html#ga0044b3d448765635208740af525b7f8f">More...</a><br/></td></tr>
<tr class="separator:ga0044b3d448765635208740af525b7f8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5a70be53ce33122f5cc5d0f4d0450bf6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga5a70be53ce33122f5cc5d0f4d0450bf6">XCSITX_LCSTAT_VC1_IER_MASK</a>&#160;&#160;&#160;(1&lt;&lt;10)</td></tr>
<tr class="memdesc:ga5a70be53ce33122f5cc5d0f4d0450bf6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC1 IER.  <a href="group__csi2tx.html#ga5a70be53ce33122f5cc5d0f4d0450bf6">More...</a><br/></td></tr>
<tr class="separator:ga5a70be53ce33122f5cc5d0f4d0450bf6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaffcbe2e0effcbd2ff9806e9e28ebf26"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#gaaffcbe2e0effcbd2ff9806e9e28ebf26">XCSITX_LCSTAT_VC2_IER_MASK</a>&#160;&#160;&#160;(1&lt;&lt;12)</td></tr>
<tr class="memdesc:gaaffcbe2e0effcbd2ff9806e9e28ebf26"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC2 IER.  <a href="group__csi2tx.html#gaaffcbe2e0effcbd2ff9806e9e28ebf26">More...</a><br/></td></tr>
<tr class="separator:gaaffcbe2e0effcbd2ff9806e9e28ebf26"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0bd1beb0451ef2e16f517a7933069e68"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga0bd1beb0451ef2e16f517a7933069e68">XCSITX_LCSTAT_VC3_IER_MASK</a>&#160;&#160;&#160;(1&lt;&lt;14)</td></tr>
<tr class="memdesc:ga0bd1beb0451ef2e16f517a7933069e68"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC3 IER.  <a href="group__csi2tx.html#ga0bd1beb0451ef2e16f517a7933069e68">More...</a><br/></td></tr>
<tr class="separator:ga0bd1beb0451ef2e16f517a7933069e68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga10a735a664b23493bbcfe038e7fc5090"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga10a735a664b23493bbcfe038e7fc5090">XCSITX_LCSTAT_VC0_IER_OFFSET</a>&#160;&#160;&#160;(8)</td></tr>
<tr class="memdesc:ga10a735a664b23493bbcfe038e7fc5090"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC0 IER Offset.  <a href="group__csi2tx.html#ga10a735a664b23493bbcfe038e7fc5090">More...</a><br/></td></tr>
<tr class="separator:ga10a735a664b23493bbcfe038e7fc5090"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3edc584a66bd4eec9e3d7f9527688719"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga3edc584a66bd4eec9e3d7f9527688719">XCSITX_LCSTAT_VC1_IER_OFFSET</a>&#160;&#160;&#160;(10)</td></tr>
<tr class="memdesc:ga3edc584a66bd4eec9e3d7f9527688719"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC1 IER Offset.  <a href="group__csi2tx.html#ga3edc584a66bd4eec9e3d7f9527688719">More...</a><br/></td></tr>
<tr class="separator:ga3edc584a66bd4eec9e3d7f9527688719"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4b50b90be1a5046ac8620ce35a8316e0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga4b50b90be1a5046ac8620ce35a8316e0">XCSITX_LCSTAT_VC2_IER_OFFSET</a>&#160;&#160;&#160;(12)</td></tr>
<tr class="memdesc:ga4b50b90be1a5046ac8620ce35a8316e0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC2 IER Offset.  <a href="group__csi2tx.html#ga4b50b90be1a5046ac8620ce35a8316e0">More...</a><br/></td></tr>
<tr class="separator:ga4b50b90be1a5046ac8620ce35a8316e0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga751e5c1a5b8ba04269280f5006b5b4e9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga751e5c1a5b8ba04269280f5006b5b4e9">XCSITX_LCSTAT_VC3_IER_OFFSET</a>&#160;&#160;&#160;(14)</td></tr>
<tr class="memdesc:ga751e5c1a5b8ba04269280f5006b5b4e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC3 IER Offset.  <a href="group__csi2tx.html#ga751e5c1a5b8ba04269280f5006b5b4e9">More...</a><br/></td></tr>
<tr class="separator:ga751e5c1a5b8ba04269280f5006b5b4e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga142de52fd9fccd7f077ffa5a6d595aea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga142de52fd9fccd7f077ffa5a6d595aea">XCSITX_LCSTAT_VC0_ISR_MASK</a>&#160;&#160;&#160;(0x3&lt;&lt;8)</td></tr>
<tr class="memdesc:ga142de52fd9fccd7f077ffa5a6d595aea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC0 ISR.  <a href="group__csi2tx.html#ga142de52fd9fccd7f077ffa5a6d595aea">More...</a><br/></td></tr>
<tr class="separator:ga142de52fd9fccd7f077ffa5a6d595aea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga987e9104d3d2c47d0a4241029df51d67"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga987e9104d3d2c47d0a4241029df51d67">XCSITX_LCSTAT_VC1_ISR_MASK</a>&#160;&#160;&#160;(0x3&lt;&lt;10)</td></tr>
<tr class="memdesc:ga987e9104d3d2c47d0a4241029df51d67"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC1 ISR.  <a href="group__csi2tx.html#ga987e9104d3d2c47d0a4241029df51d67">More...</a><br/></td></tr>
<tr class="separator:ga987e9104d3d2c47d0a4241029df51d67"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga61d9538e0d010ffb6dc990475372fefb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga61d9538e0d010ffb6dc990475372fefb">XCSITX_LCSTAT_VC2_ISR_MASK</a>&#160;&#160;&#160;(0x3&lt;&lt;12)</td></tr>
<tr class="memdesc:ga61d9538e0d010ffb6dc990475372fefb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC2 ISR.  <a href="group__csi2tx.html#ga61d9538e0d010ffb6dc990475372fefb">More...</a><br/></td></tr>
<tr class="separator:ga61d9538e0d010ffb6dc990475372fefb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae0bb66a7b93fa93e9ae7126a9e7c2397"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#gae0bb66a7b93fa93e9ae7126a9e7c2397">XCSITX_LCSTAT_VC3_ISR_MASK</a>&#160;&#160;&#160;(0x3&lt;&lt;14)</td></tr>
<tr class="memdesc:gae0bb66a7b93fa93e9ae7126a9e7c2397"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC3 ISR.  <a href="group__csi2tx.html#gae0bb66a7b93fa93e9ae7126a9e7c2397">More...</a><br/></td></tr>
<tr class="separator:gae0bb66a7b93fa93e9ae7126a9e7c2397"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga286313baf965deb60dec63793619c051"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga286313baf965deb60dec63793619c051">XCSITX_LCSTAT_VC0_ISR_OFFSET</a>&#160;&#160;&#160;(8)</td></tr>
<tr class="memdesc:ga286313baf965deb60dec63793619c051"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC0 ISR Offset.  <a href="group__csi2tx.html#ga286313baf965deb60dec63793619c051">More...</a><br/></td></tr>
<tr class="separator:ga286313baf965deb60dec63793619c051"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf1a83a4df52d05590aa4f2f6e3c20a6c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#gaf1a83a4df52d05590aa4f2f6e3c20a6c">XCSITX_LCSTAT_VC1_ISR_OFFSET</a>&#160;&#160;&#160;(10)</td></tr>
<tr class="memdesc:gaf1a83a4df52d05590aa4f2f6e3c20a6c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC1 ISR Offset.  <a href="group__csi2tx.html#gaf1a83a4df52d05590aa4f2f6e3c20a6c">More...</a><br/></td></tr>
<tr class="separator:gaf1a83a4df52d05590aa4f2f6e3c20a6c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3ee9d8a174df41745968a05430f3a604"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga3ee9d8a174df41745968a05430f3a604">XCSITX_LCSTAT_VC2_ISR_OFFSET</a>&#160;&#160;&#160;(12)</td></tr>
<tr class="memdesc:ga3ee9d8a174df41745968a05430f3a604"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC2 ISR Offset.  <a href="group__csi2tx.html#ga3ee9d8a174df41745968a05430f3a604">More...</a><br/></td></tr>
<tr class="separator:ga3ee9d8a174df41745968a05430f3a604"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga945d23526f204191f2d579e9169105d8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csi2tx.html#ga945d23526f204191f2d579e9169105d8">XCSITX_LCSTAT_VC3_ISR_OFFSET</a>&#160;&#160;&#160;(14)</td></tr>
<tr class="memdesc:ga945d23526f204191f2d579e9169105d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Count Status for VC3 ISR Offset.  <a href="group__csi2tx.html#ga945d23526f204191f2d579e9169105d8">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">BitMasks Short Packets</div></td></tr>
<tr class="memitem:ga2edf8b9efa772fbbf6f9b59c8a62ae4e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2edf8b9efa772fbbf6f9b59c8a62ae4e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_SPKTR_DATA_MASK</b>&#160;&#160;&#160;0x00FFFF00 /* Short Packet byte0 and 1*/</td></tr>
<tr class="separator:ga2edf8b9efa772fbbf6f9b59c8a62ae4e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae7f2e4bcb9b0f9cc88d9a4d20dfaac08"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae7f2e4bcb9b0f9cc88d9a4d20dfaac08"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_SPKTR_DATA_SHIFT</b>&#160;&#160;&#160;8</td></tr>
<tr class="separator:gae7f2e4bcb9b0f9cc88d9a4d20dfaac08"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga393a6fa1172d8460c7966eb9f70f88f0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga393a6fa1172d8460c7966eb9f70f88f0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_SPKTR_VC_MASK</b></td></tr>
<tr class="separator:ga393a6fa1172d8460c7966eb9f70f88f0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8b54de5bbedc4ddca730d8cf3eaa5c39"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8b54de5bbedc4ddca730d8cf3eaa5c39"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_SPKTR_VC_SHIFT</b>&#160;&#160;&#160;6</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_SPKTR_DT_MASK</b>&#160;&#160;&#160;0x0000003F /* Short Packet Data type*/</td></tr>
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<tr class="memitem:gae5791af5ed0f79ecf141225536ddf4eb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae5791af5ed0f79ecf141225536ddf4eb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCSI2TX_SPKTR_DT_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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